1. Field of the Invention
The invention relates in general to a capacitance measurement circuit and a capacitance measurement method, and more particularly to a capacitance measurement circuit using a continuous time integrator, and a capacitance measurement method thereof.
2. Description of the Related Art
FIGS. 1 and 2 (Prior Art) are circuit diagrams showing conventional capacitance measurement circuits 10 and 20. Referring to FIGS. 1 and 2, each of the conventional capacitance measurement circuits 10 and 20 is for measuring a capacitance variation of a capacitor Cz under test and converts the capacitance variation into a digital signal for output. The capacitor Cz under test is a capacitor whose capacitance changes when the capacitor is triggered. For example, the capacitance of a sensing line of a capacitive touch screen in the X direction or Y direction is changed when being touched by a conductor. A capacitor array 150 has the capacitance, which may be selected via a switch, and provides an equivalent capacitor CR, wherein a capacitor Cc has the known capacitance.
VY is integrated in an integrating clock signal period NS being set according to the time when the capacitor Cz under test cannot be triggered, and a comparison signal CMPO outputted from the comparator CMP is read after the charging clock signal period NS being set has elapsed. If the capacitance of the capacitor Cz is smaller than that of the equivalent capacitor CR, the comparison signal CMPO outputted from the comparator CMP is low, and a control logic 110 decreases the capacitance of the equivalent capacitor CR of the capacitor array 150. Oppositely, if the capacitance of the capacitor Cz is larger than that of the equivalent capacitor CR of the capacitor array 150, the comparison signal CMPO outputted from the comparator CMP is high, and the control logic 110 increases the capacitance of the equivalent capacitor CR of the capacitor array 150. The above-mentioned procedures are repeated until the capacitance setting value of the capacitor array 150 is as that the comparison signal CMPO is low when the minimum unit capacitance that may be adjusted in the capacitor array 150 is increased, and the comparison signal CMPO is high when the minimum unit capacitance is decreased, and sets this capacitance setting value as the capacitance setting value of the capacitor array 150 for measuring the capacitance variation of the capacitor Cz. After the capacitance of the capacitor array 150 is selected, the capacitance variation of the capacitor Cz under test may be measured.
The conventional capacitance measurement circuit 10 adopts the dual slope method to obtain the changed capacitance equal to ND/NC*Cc after being triggered according to the capacitance difference between the capacitor Cz under test and the equivalent capacitor CR, the integrating clock signal period NC, and the clock signal period ND calculated by the counter 120 when the capacitor Cc is reversely integrated.
The conventional capacitance measurement circuit 20 adopts the sigma-delta method. At the beginning, VY is set to be a reference voltage V1. If the comparison signal CMPO outputted from the comparator CMP is high, the signal CE outputted from the control logic 110 is high, and the 1-bit signal is transferred to the input terminal of a digital filter 160. The capacitor Cc starts to integrate VY reversely to reduce V. When VY is lower than the negative end input voltage V1 of the comparator CMP, the comparison signal CMPO outputted from the comparator CMP becomes low, and the signal CE outputted from the control logic 110 is low. In this case, the capacitance difference between the capacitor Cz and the equivalent capacitor CR starts to integrate VY positively so that VY is gradually increased. When VY is higher than the comparator negative end input voltage V1, the comparison signal CMPO outputted from the comparator CMP becomes high, and the above-mentioned procedures are repeated. Consequently, the digital filter 160 filters out the values of the high and low 1-bit signals of the series of signals CE other than the DC components, the capacitance difference between the capacitor Cz and the equivalent capacitor CR can be obtained according to the digital output of the digital filter 160.
Each of the conventional capacitance measurement circuits 10 and 20 can measure the increased or decreased variation of the capacitance of the triggered capacitor Cz under test. The condition of V1>V2 is selected if the increased capacitance variation is to be measured after the capacitor Cz under test is triggered; and the condition of V1<V2 is selected if the decreased capacitance variation is to be measured.
However, each of the conventional capacitance measurement circuits 10 and 20 shown in FIGS. 1 and 2 tends to be influenced by the switch noise, and a set of oscillators have to be additionally provided so that the manufacturing cost is increased.